1. Field of the Invention
The present invention relates to a method of driving an organic electroluminescence display apparatus.
2. Description of the Related Art
A display element having a light-emitting portion and a display apparatus having the display elements are known well. For example, display elements (hereinafter, also referred to as “organic EL display elements”) having an organic electroluminescence (hereinafter, also abbreviated as “EL”) light-emitting portion using the electroluminescence phenomenon of an organic material attract attention as display elements capable of emitting light with high luminance by low-voltage DC driving.
In an organic EL display apparatus having organic EL display elements, such as a liquid crystal display apparatus, a simple matrix driving method and an active matrix driving method are known well as a driving method. The active matrix driving method has a disadvantage that the structure is complicated but has an advantage that it can enhance the luminance of an image. The organic EL display element driven in the active matrix driving method should have a driving circuit driving a light-emitting portion in addition to the light-emitting portion formed of an organic layer including a light-emitting layer.
As a circuit driving an organic EL light-emitting portion (hereinafter, also referred to as “light-emitting portion”), a driving circuit (referred to as “2Tr/1C driving circuit”) including two transistors and one capacitor is disclosed, for example, in Japanese Unexamined Patent Application Publication No. 2007-310311. As shown in FIG. 2, the 2Tr/1C driving circuit includes two transistors these being a writing transistor TRW and a driving transistor TRD and one capacitor C1. Here, one of source and drain regions of the driving transistor TRD forms a second node ND2 and the gate electrode of the driving transistor TRD forms a first node ND1.
As shown in the timing diagram of FIG. 4, a preprocessing process of a threshold voltage canceling process is performed in period TP(2)1′. That is, a first node initialization voltage VOfs (for example, 0 V) is applied to the first node ND1 from a data line DTL via the writing transistor TRW turned on by a signal from a scanning line SCL. Accordingly, the potential of the first node ND1 is VOfs. A second node initialization voltage VCC-L (for example, −10 V) is applied to the second node ND2 from a power source unit 100 via the driving transistor TRD. Accordingly, the potential of the second node ND2 is VCC-L. The threshold voltage of the driving transistor TRD is represented by Vth (for example, 3 V). The potential difference between the gate electrode of the driving transistor TRD and the other of the source and drain regions (hereinafter, also referred to as source region for the purpose of convenience) thereof is equal to or greater than Vth and the driving transistor TRD is thus turned on. A cathode of the light-emitting portion ELP is connected to a power supply line PS2 through which a voltage VCat (for example, 0 V) is applied.
Then, in period TP(2)2′, the threshold voltage canceling process is performed. That is, with the writing transistor TRW kept in the ON state, the voltage of the power source unit 100 is switched from the second node initialization voltage VCC-L to a driving voltage VCC-H (for example, 20 V). As a result, the potential of the second node ND2 varies to the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD from the potential of the first node ND1. That is, the potential of the second node ND2 in a floating state increases. When the potential difference between the gate electrode of the driving transistor TRD and the source region reaches Vth, the driving transistor TRD is turned off. In this state, the potential of the second node ND2 is about (VOfs−Vth).
Thereafter, in period TP(2)3′, the writing transistor TRW is turned off. The voltage of the data line DTL is changed to the voltage (the image signal (driving signal, luminance signal) VSig—m for controlling the luminance of the light-emitting portion ELP) corresponding to the image signal.
Then, in period TP(2)4′, a writing process is performed. Specifically, the writing transistor TRW is turned on by setting the scanning line SCL to a high level. As a result, the potential of the first node ND1 increases to the image signal VSig—m.
Here, the value of the capacitor C1 is set to c1 and the value of the capacitor CEL of the light-emitting portion ELP is set to cEL. The parasitic capacitance value between the gate electrode of the driving transistor TRD and the other of the source and drain regions is set to cgs. When the potential of the gate electrode of the driving transistor TRD is changed from VOfs to VSig—m (>VOfs), the potential between both electrodes of the capacitor C1 (that is, the potential between the first node ND1 and the second node ND2) is also changed in principle. That is, electric charges based on the variation (VSig—m−VOfs) in the potential of the gate electrode (=the potential of the first node ND1) of the driving transistor TRD are distributed to the capacitor C1, the capacitor CEL of the light-emitting portion ELP, and the parasitic capacitor between the gate electrode of the driving transistor TRD and the other of the source and drain regions. When the value of cEL is much greater than the value of c1 and the value of cgs, the variation in potential of the other (second node ND2) of the source and drain regions of the driving transistor TRD based on the variation in potential (VSig—m−VOfs) of the gate electrode of the driving transistor TRD is small. In general, the value cEL of the capacitor CEL of the light-emitting portion ELP is greater than the value c1 of the capacitor C1 and the value cgs of the parasitic capacitor of the driving transistor TRD. Accordingly, for the purpose of simplifying the explanation, the variation in potential of the second node ND2 resulting from the variation in potential of the first node ND1 is not considered in the following description. In the driving timing diagram shown in FIG. 4, the variation in potential of the second node ND2 resulting from the variation in potential of the first node ND1 is not considered.
In the above-mentioned operations, in a state where the voltage VCC-H is applied to one of the source and drain regions of the driving transistor TRD from the power source unit 100, the image signal VSig—m is applied to the gate electrode of the driving transistor TRD. Accordingly, as shown in FIG. 4, the potential of the second node ND2 increases in period TP(2)4′. The amount of increasing potential ΔV (potential correcting value) will be described later. When the potential of the gate electrode (first node ND1) of the driving transistor TRD is Vg and the potential of the other of the source and drain regions (second node ND2) is Vs, the value of Vg and the value of Vs are as follows without considering the amount of increasing potential ΔV of the second node ND2. The potential difference between the first node ND1 and the second node ND2, that is, the potential difference Vgs between the gate electrode of the driving transistor TRD and the other of the source and drain regions serving as the source region, can be expressed by Expression A.Vg=VSig—m Vs≅VOfs−Vth Vgs≅VSig—m−(VOfs−Vth)  Expression A
That is, Vgs obtained in the writing process on the driving transistor TRD depends on only on the image signal VSig—m for controlling the luminance of the light-emitting portion ELP, the threshold voltage Vth of the driving transistor TRD, and the voltage VOfs for initializing the potential of the gate electrode of the driving transistor TRD. The value Vgs does not depend on the threshold voltage Vth-EL of the light-emitting portion ELP.
A mobility correcting process will be described now in brief. In the above-mentioned operation, the mobility correcting process of changing the potential (that is, the potential of the second node ND2) of the other of the source and drain regions of the driving transistor TRD depending on the characteristic of the driving transistor TRD (for example, the magnitude of the mobility μ) is performed along with the writing process.
As described above, in a state where the voltage VCC-H is applied to one of the source and drain regions of the driving transistor TRD from the power source unit 100, the image signal VSig—m is applied to the gate electrode of the driving transistor TRD. Here, as shown in FIG. 4, the potential of the second node ND2 increases in period TP(2)4′. As a result, the amount of increasing potential ΔV (potential correcting value) in the source region of the driving transistor TRD increases when the value of the mobility μ of the driving transistor TRD is great, and the amount of increasing potential ΔV (potential correcting value) in the source region of the driving transistor TRD decreases when the value of the mobility μ of the driving transistor TRD is small. The potential difference Vgs between the gate electrode of the driving transistor TRD and the source region is changed from Expression A to Expression B. The entire time (t0) of period TP(2)4′ can be determined in advance as a design value at the time of designing the organic EL display apparatus.Vgs≅VSig—m−(VOfs−Vth)−ΔV  Expression B
The threshold voltage canceling process, the writing process, and the mobility correcting process are finished by the above-mentioned operations. At the start time of period TP(2)5′, the first node ND1 is changed to a floating state by turning off the writing transistor TRW on the basis of the signal from the scanning line SCL. The voltage VCC-H is applied to one (hereinafter, also referred to as drain region for convenience) of the source and drain regions of the driving transistor TRD from the power source unit 100. As a result, the potential of the second node ND2 increases, the same phenomenon as that in a so-called bootstrap circuit occurs in the gate electrode of the driving transistor TRD, and thus the potential of the first node ND1 also increases. The potential difference Vgs between the gate electrode and the source region of the driving transistor TRD holds the value of Expression B. The current flowing in the light-emitting portion ELP is a drain current Ids flowing from the drain region of the driving transistor TRD to the source region. When the driving transistor TRD ideally operates in a saturated region, the drain current Ids can be expressed by Expression C. The light-emitting portion ELP emits light with the luminance corresponding to the value of the drain current Ids. The coefficient k will be described later.Ids=k·μ·(Vgs−Vth)2 =k·μ·(VSig—m−VOfs−ΔV)2  Expression C
Period TP(2)5′ shown in FIG. 4 is called an emission period and a period of time from the start of period TP(2)6′ to the next emission period is called a period of a non-emission state (hereinafter, also simply referred to as non-emission period). Specifically, at the start time of period TP(2)6′, the voltage VCC-H of the power source unit 100 is switched to the voltage VCC-L, which is maintained up to the end time of next period TP(2)1′ (shown by period TP(2)+1′ in FIG. 4). Accordingly, the period of time from the start of period TP(2)6′ to next period TP(2)+5′ is a non-emission period.
The operation of the 2Tr/1C driving circuit of which the configuration has been schematically described above will be described in detail later.